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公开(公告)号：US20240303409A1
公开(公告)日：2024-09-12
申请号：US18669864
申请日：2024-05-21
发明人： Shin-Chi Chen , King-Ho Tam , Yu-Ze Lin , Huang-Yu Chen
IPC分类号： G06F30/392 , G06F30/31 , G06F30/327 , G06F119/18
CPC分类号： G06F30/392 , G06F30/31 , G06F30/327 , G06F2119/18
摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.
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公开(公告)号：US11907007B2
公开(公告)日：2024-02-20
申请号：US17140399
申请日：2021-01-04
发明人： Jerry Chang Jui Kao , Huang-Yu Chen , Sheng-Hsiung Chen , Jack Liu , Yung-Chen Chien , Wei-Hsiang Ma , Chung-Hsing Wang
IPC分类号： G06F1/10 , G06F30/396
CPC分类号： G06F1/10 , G06F30/396
摘要： A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.
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公开(公告)号：US11715733B2
公开(公告)日：2023-08-01
申请号：US17313474
申请日：2021-05-06
发明人： Wei-Ren Chen , Cheng-Yu Lin , Hui-Zhong Zhuang , Yung-Chen Chien , Jerry Chang Jui Kao , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： H01L27/02 , H01L27/092 , G06F30/394 , H01L21/8238 , G06F30/392 , H01L23/522
CPC分类号： H01L27/0207 , G06F30/392 , G06F30/394 , H01L21/823871 , H01L23/5226 , H01L27/092
摘要： An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.
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公开(公告)号：US11669669B2
公开(公告)日：2023-06-06
申请号：US16943827
申请日：2020-07-30
发明人： Chin-Shen Lin , Wan-Yu Lo , Shao-Huan Wang , Kuo-Nan Yang , Chung-Hsing Wang , Sheng-Hsiung Chen , Huang-Yu Chen
IPC分类号： G06F30/30 , G06F30/392 , G06F30/347 , H01L21/78
CPC分类号： G06F30/392 , G06F30/347 , H01L21/78
摘要： A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.
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公开(公告)号：US09754073B2
公开(公告)日：2017-09-05
申请号：US15237286
申请日：2016-08-15
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
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公开(公告)号：US08898600B2
公开(公告)日：2014-11-25
申请号：US13941941
申请日：2013-07-15
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F7/0035 , G06F17/5072 , G06F2217/08 , G06F2217/12
摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
摘要翻译： 布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束 出区。 目标图案应形成相应的主要特征和切割图案。
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公开(公告)号：US11620426B2
公开(公告)日：2023-04-04
申请号：US17331825
申请日：2021-05-27
发明人： Shin-Chi Chen , King-Ho Tam , Yu-Ze Lin , Huang-Yu Chen
IPC分类号： G06F30/30 , G06F30/392 , G06F30/327 , G06F30/31 , G06F119/18
摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.
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公开(公告)号：US20230023165A1
公开(公告)日：2023-01-26
申请号：US17937654
申请日：2022-10-03
IPC分类号： G06F30/3947 , G06F30/39
摘要： The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
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公开(公告)号：US20150095870A1
公开(公告)日：2015-04-02
申请号：US14564934
申请日：2014-12-09
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译： 半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。 单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。 在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。
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公开(公告)号：US20140282306A1
公开(公告)日：2014-09-18
申请号：US13941941
申请日：2013-07-15
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F7/0035 , G06F17/5072 , G06F2217/08 , G06F2217/12
摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
摘要翻译： 布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束 出区。 目标图案应形成相应的主要特征和切割图案。
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