发明授权
US09425319B2 Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
有权
集成电路包括具有较低接触电阻和降低的寄生电容的FINFET器件及其制造方法
- 专利标题： Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
- 专利标题（中）： 集成电路包括具有较低接触电阻和降低的寄生电容的FINFET器件及其制造方法
-
申请号： US14551606申请日： 2014-11-24
-
公开(公告)号： US09425319B2公开(公告)日： 2016-08-23
- 发明人: Xiuyu Cai , Ruilong Xie , Ali Khakifirooz , Kangguo Cheng
- 申请人： GLOBALFOUNDRIES, Inc. , International Business Machines Corporation
- 申请人地址： KY Grand Cayman US NY Armonk
- 专利权人： GLOBALFOUNDRIES, INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： GLOBALFOUNDRIES, INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： KY Grand Cayman US NY Armonk
- 代理机构： Ingrassia Fisher & Lorenz, P.C.
- 主分类号： H01L27/088
- IPC分类号： H01L27/088 ; H01L29/06 ; H01L29/417 ; H01L29/45 ; H01L29/78 ; H01L21/28 ; H01L29/66 ; H01L21/8234
摘要：
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.
公开/授权文献
信息查询
IPC分类:
