Invention Grant
US09430014B2 System and method for idle state optimization in a multi-processor system on a chip
有权
在芯片上的多处理器系统中空闲状态优化的系统和方法
- Patent Title: System and method for idle state optimization in a multi-processor system on a chip
- Patent Title (中): 在芯片上的多处理器系统中空闲状态优化的系统和方法
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Application No.: US13945181Application Date: 2013-07-18
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Publication No.: US09430014B2Publication Date: 2016-08-30
- Inventor: Ankur Jain , Unnikrishnan Vadakkanmaruveedu , Vinay Mitter , Henri Begin , Praveen Chidambaram
- Applicant: Qualcomm Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Smith Tempel
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
Various embodiments of methods and systems for idle state optimization in a portable computing device (“PCD”) are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload.
Public/Granted literature
- US20150026495A1 SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP Public/Granted day:2015-01-22
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