Invention Grant
US09431063B2 Stacked memory having same timing domain read data and redundancy
有权
具有相同定时域的堆叠存储器读取数据和冗余
- Patent Title: Stacked memory having same timing domain read data and redundancy
- Patent Title (中): 具有相同定时域的堆叠存储器读取数据和冗余
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Application No.: US14827831Application Date: 2015-08-17
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Publication No.: US09431063B2Publication Date: 2016-08-30
- Inventor: Frederick A. Ware , Paul D. Franzon
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Peninsula Patent Group
- Agent Lance M. Kreisman
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C5/02 ; G11C29/00 ; H01L23/538 ; G11C7/22 ; G11C11/4076

Abstract:
A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.
Public/Granted literature
- US20150357002A1 STACKED MEMORY WITH REDUNDANCY Public/Granted day:2015-12-10
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