Invention Grant
US09431063B2 Stacked memory having same timing domain read data and redundancy 有权
具有相同定时域的堆叠存储器读取数据和冗余

Stacked memory having same timing domain read data and redundancy
Abstract:
A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.
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