公开(公告)号：US20140376364A1

公开(公告)日：2014-12-25

申请号：US14236572

申请日：2012-07-20

Applicant: RAMBUS INC.

Inventor： Paul D. Franzon ,  John Wilson

IPC: H04L12/24 ,  H04L1/22 ,  H04L1/00

CPC classification number: H04L41/0686 ,  G06F11/2007 ,  H03L7/18 ,  H03L7/23 ,  H04L1/0002 ,  H04L1/22 ,  H04L41/0659 ,  H04L41/0668

Abstract: A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.

Abstract translation: 提供电路以便于芯片间通信的时间冗余。 当芯片间通信信道发生故障时，与故障信道相关联的数据比特被引导到非故障信道，并且以增加的数据速率与非故障信道相关联的数据比特通过非故障信道发送。

公开(公告)号：US20140321186A1

公开(公告)日：2014-10-30

申请号：US14319544

申请日：2014-06-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C5/02 ,  H01L23/538 ,  G11C29/00

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US20130176763A1

公开(公告)日：2013-07-11

申请号：US13728330

申请日：2012-12-27

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path.

Abstract translation: 公开了一种堆叠式存储器，其包括具有第一存储位置并与第二集成电路存储器芯片堆叠的第一集成电路存储器芯片。 冗余存储器由第一和第二集成电路存储器芯片共享，并且具有选择性地替换第一或第二集成电路存储器芯片中的相应存储位置的冗余存储位置。 堆叠式存储器还包括用于耦合到外部集成电路存储器控制器和相应的第一和第二信号路径的引脚接口。 第一信号路径通过第一和第二集成电路存储器芯片形成，并且耦合到冗余存储器和引脚接口。 第二信号路径通过第一和第二集成电路存储器芯片形成，并且经由第一信号路径耦合到冗余存储器和引脚接口。

公开(公告)号：US09431063B2

公开(公告)日：2016-08-30

申请号：US14827831

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C8/00 ,  G11C5/02 ,  G11C29/00 ,  H01L23/538 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US20150357002A1

公开(公告)日：2015-12-10

申请号：US14827831

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C5/02 ,  G11C29/00

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US09111587B2

公开(公告)日：2015-08-18

申请号：US14319544

申请日：2014-06-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C7/00 ,  G11C5/02 ,  G11C29/00 ,  H01L23/538

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US08804394B2

公开(公告)日：2014-08-12

申请号：US13728330

申请日：2012-12-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path.

Abstract translation: 公开了一种堆叠式存储器，其包括具有第一存储位置并与第二集成电路存储器芯片堆叠的第一集成电路存储器芯片。 冗余存储器由第一和第二集成电路存储器芯片共享，并且具有选择性地替换第一或第二集成电路存储器芯片中的相应存储位置的冗余存储位置。 堆叠式存储器还包括用于耦合到外部集成电路存储器控制器和相应的第一和第二信号路径的引脚接口。 第一信号路径通过第一和第二集成电路存储器芯片形成，并且耦合到冗余存储器和引脚接口。 第二信号路径通过第一和第二集成电路存储器芯片形成，并且经由第一信号路径耦合到冗余存储器和引脚接口。

公开(公告)号：US20130168674A1

公开(公告)日：2013-07-04

申请号：US13719724

申请日：2012-12-19

Applicant: Rambus Inc.

Inventor： Paul D. Franzon ,  Thomas Vogelsang ,  Frederick A. Ware ,  Wayne Ellis

IPC: H01L23/48 ,  H01L27/10

CPC classification number: H01L23/481 ,  G11C7/1045 ,  G11C29/006 ,  G11C29/785 ,  G11C29/816 ,  G11C29/83 ,  H01L22/34 ,  H01L23/5256 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active devices, and is therefore relatively reliable and inexpensive.

Abstract translation: 三维集成电路（3D-IC）包括一堆半导体晶片，每个半导体晶片包括基板和器件层。 可编程组件，例如存储器阵列或逻辑电路，在器件层内形成。 一些可编程组件是冗余的，并且可以通过在为此目的提供的单独导电层中编程无源存储器元件来代替有缺陷的组件。 单独的导电层没有有源器件，因此是相对可靠和便宜的。