Invention Grant
- Patent Title: Data line arrangement and pillar arrangement in apparatuses
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Application No.: US14850781Application Date: 2015-09-10
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Publication No.: US09431421B2Publication Date: 2016-08-30
- Inventor: Luyen Vu , Mark A. Helm
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L29/16 ; H01L29/04

Abstract:
Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).
Public/Granted literature
- US20160005761A1 Data Line Arrangement and Pillar Arrangement in Apparatuses Public/Granted day:2016-01-07
Information query
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