Invention Grant
- Patent Title: DRAM sense amplifier that supports low memory-cell capacitance
- Patent Title (中): 支持低存储单元电容的DRAM读出放大器
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Application No.: US14506507Application Date: 2014-10-03
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Publication No.: US09437280B2Publication Date: 2016-09-06
- Inventor: Thomas Vogelsang , Gary B. Bronner
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/4091 ; G11C7/06 ; G11C7/08 ; G11C11/4094 ; G11C11/4096 ; H01L27/108

Abstract:
The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.
Public/Granted literature
- US20150103605A1 DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE Public/Granted day:2015-04-16
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