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    Pulse Control For Non-Volatile Memory
    1.
    发明申请
    Pulse Control For Non-Volatile Memory 有权
    非易失性存储器的脉冲控制

    公开(公告)号：US20160027515A1

    公开(公告)日：2016-01-28

    申请号：US14878902

    申请日：2015-10-08

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  Brent Steven Haukness ,  Gary B. Bronner ,  Kevin Donnelly

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459

    Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

    Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

    DRAM sense amplifier that supports low memory-cell capacitance
    2.
    发明授权
    DRAM sense amplifier that supports low memory-cell capacitance 有权
    支持低存储单元电容的DRAM读出放大器

    公开(公告)号：US09437280B2

    公开(公告)日：2016-09-06

    申请号：US14506507

    申请日：2014-10-03

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Gary B. Bronner

    IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/108

    CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10873 ,  H01L27/10897

    Abstract: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.

    Abstract translation: 所公开的实施例提供用于动态随机存取存储器（DRAM）的读出放大器。 该读出放大器包括要耦合到要在DRAM中感测的单元的位线以及在位线上承载信号的补码的补码位线。 读出放大器还包括p型场效应晶体管（PFET）对，其包括选择性地将位线或补码位线耦合到高位线电压的交叉耦合PFET。 读出放大器另外包括n型场效应晶体管（NFET）对，其包括交叉耦合NFET，其选择性地将位线或补码位线耦合到地。 该NFET对被轻掺杂以在NFET对中的NFET之间提供低阈值电压失配。 在一个实施例中，用于NFET的栅极材料被选择为具有补偿由于衬底掺杂导致的NFET中的负阈值电压的功函数。 在另一变型中，读出放大器另外包括交叉耦合的一对锁存NFET。 这些锁存NFET通常是掺杂的，并且被配置为在轻掺杂NFET完成感测位线上的电压之后锁存位线上的电压。

    DYNAMIC MEMORY RANK CONFIGURATION
    3.
    发明申请
    DYNAMIC MEMORY RANK CONFIGURATION 审中-公开
    动态记忆排名配置

    公开(公告)号：US20160071608A1

    公开(公告)日：2016-03-10

    申请号：US14940084

    申请日：2015-11-12

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent S. Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/06 ,  H01L21/324

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    Abstract translation: 存储器控制组件内的控制逻辑在相应的时间向存储器模块输出第一和第二存储器读取命令，存储器模块具有置于其上的存储器组件。 存储器控制组件内的接口电路响应于第一存储器读取命令分别经由第一多个数据路径从第一多个存储器组件同时接收第一读取数据，并且从第二个多个 所述存储器组件分别响应于所述第二存储器读取命令经由第二多个数据路径，所述第一多个存储器组件包括不包括在所述第二多个存储器组件中的至少一个存储器组件，反之亦然。

    System and Method for Writing Data to an RRAM Cell
    5.
    发明申请
    System and Method for Writing Data to an RRAM Cell 审中-公开
    将数据写入RRAM单元的系统和方法

    公开(公告)号：US20130250657A1

    公开(公告)日：2013-09-26

    申请号：US13789543

    申请日：2013-03-07

    Applicant: Rambus Inc.

    Inventor： Brent Steven Haukness ,  Mark D. Kellam ,  Gary B. Bronner ,  Craig Hampel

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/79

    Abstract: A resistive RAM device includes a bit line, a word line, an RRAM cell coupled to the word line and to the bit line, a write driver and a disable circuit. The write driver is coupled to the bit line. The disable circuit stops a write operation performed by the write driver on a respective RRAM cell when a predefined condition on the bit line is achieved. The predefined condition depends on a mode of operation of the RRAM cell.

    Abstract translation: 电阻RAM装置包括位线，字线，耦合到字线和位线的RRAM单元，写驱动器和禁止电路。 写驱动器耦合到位线。 当实现位线上的预定义条件时，禁止电路在相应的RRAM单元上停止由写入驱动器执行的写入操作。 预定义条件取决于RRAM单元的操作模式。

    SOLID-STATE DRIVE WITH THERMAL ANNEAL FUNCTION
    6.
    发明申请
    SOLID-STATE DRIVE WITH THERMAL ANNEAL FUNCTION 有权

    公开(公告)号：US20240395327A1

    公开(公告)日：2024-11-28

    申请号：US18645875

    申请日：2024-04-25

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent Steven Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/06 ,  G11C7/04 ,  G11C13/00 ,  G11C16/26 ,  H01L21/324

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    Reduced refresh power
    8.
    发明授权
    Reduced refresh power 有权
    降低刷新功率

    公开(公告)号：US09490002B2

    公开(公告)日：2016-11-08

    申请号：US14801558

    申请日：2015-07-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Scott C. Best ,  Gary B. Bronner

    IPC: G11C7/00 ,  G11C11/406

    CPC classification number: G11C11/40611 ,  G11C2211/4061

    Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.

    Abstract translation: 每个M个刷新命令中的N个被存储器模块上的缓冲器芯片忽略（滤除掉）。 N和M是可编程的。 缓冲器从命令地址信道接收刷新命令（例如，自动刷新命令），但不向模块上的DRAM发出这些命令的一部分。 这减少了刷新操作所消耗的功耗。 缓冲区可以用针对特定行的激活（ACT）和预充电（PRE）命令替换一些自动刷新（REF）命令。 这些行可能具有比模块（或组件）上的大多数其他行更频繁刷新的已知“弱”单元格。 通过忽略一些自动刷新命令，并将一些其他命令指向具有“弱”单元格的特定行，可以减少刷新操作消耗的功率。

    DYNAMIC MEMORY RANK CONFIGURATION
    9.
    发明申请
    DYNAMIC MEMORY RANK CONFIGURATION 有权

    公开(公告)号：US20220238159A1

    公开(公告)日：2022-07-28

    申请号：US17567401

    申请日：2022-01-03

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent Steven Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/06 ,  G11C13/00 ,  G11C16/26

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    Pulse control for nonvolatile memory
    10.
    发明授权
    Pulse control for nonvolatile memory 有权
    非易失性存储器的脉冲控制

    公开(公告)号：US09177655B2

    公开(公告)日：2015-11-03

    申请号：US14145962

    申请日：2014-01-01

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  Brent Steven Haukness ,  Gary B. Bronner ,  Kevin Donnelly

    IPC: G11C16/12 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459

    Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

    Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

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