Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.