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公开(公告)号：US11600665B2
公开(公告)日：2023-03-07
申请号：US17069347
申请日：2020-10-13
发明人： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
摘要： The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US20190109176A1
公开(公告)日：2019-04-11
申请号：US16212861
申请日：2018-12-07
摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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公开(公告)号：US10084016B2
公开(公告)日：2018-09-25
申请号：US14086460
申请日：2013-11-21
CPC分类号： H01L27/2463 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号：US20160104748A1
公开(公告)日：2016-04-14
申请号：US14970602
申请日：2015-12-16
CPC分类号： H01L27/2481 , G11C5/063 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1608 , H01L45/1666 , H01L45/1675
摘要： The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.
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公开(公告)号：US20150084156A1
公开(公告)日：2015-03-26
申请号：US14036788
申请日：2013-09-25
IPC分类号： H01L27/105 , H01L21/28
CPC分类号： H01L45/124 , H01L21/28 , H01L21/3213 , H01L27/1052 , H01L27/222 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
摘要翻译： 提供了存储单元结构及其形成方法。 示例性存储器单元可以包括开关元件和存储元件。 在存储元件和开关元件之间形成中间电极。 在除了存储元件和开关元件之外的位置处，在开关元件或存储元件附近形成外部电极。 中间电极的横向尺寸不同于外部电极的横向尺寸。
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公开(公告)号：US20150069630A1
公开(公告)日：2015-03-12
申请号：US14025537
申请日：2013-09-12
发明人： Samuele Sciarrillo
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76895 , H01L21/7684 , H01L27/2409 , H01L27/2427 , H01L27/2436 , H01L27/2445 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.
摘要翻译： 提供了存储单元阵列结构及其形成方法。 用于形成存储器单元阵列的示例性方法可以包括形成多个垂直结构，每个垂直结构具有与顶部电极串联的存储元件串联的开关元件，以及在多个的各个顶部电极之间形成互连导电材料 的垂直结构。 互连导电材料经过回蚀和化学机械抛光（CMPed）。 在互连导电材料CMP之后，在互连导电材料上形成导线。
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公开(公告)号：US20210091140A1
公开(公告)日：2021-03-25
申请号：US17069347
申请日：2020-10-13
发明人： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
摘要： The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US10886332B2
公开(公告)日：2021-01-05
申请号：US16736252
申请日：2020-01-07
摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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公开(公告)号：US10157965B2
公开(公告)日：2018-12-18
申请号：US15398475
申请日：2017-01-04
发明人： Samuele Sciarrillo
摘要： The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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公开(公告)号：US09831428B2
公开(公告)日：2017-11-28
申请号：US14972152
申请日：2015-12-17
IPC分类号： H01L45/00 , H01L27/105 , H01L21/28 , H01L21/3213 , H01L27/24 , H01L27/22
CPC分类号： H01L45/124 , H01L21/28 , H01L21/3213 , H01L27/1052 , H01L27/222 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
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