Invention Grant
- Patent Title: Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set
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Application No.: US12454283Application Date: 2009-05-15
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Publication No.: US09443838B2Publication Date: 2016-09-13
- Inventor: Li-Ping Yang , Pi-Cheng Chen , Han-Chang Kang , Ran-Hong Yan
- Applicant: Li-Ping Yang , Pi-Cheng Chen , Han-Chang Kang , Ran-Hong Yan
- Applicant Address: TW Hsinchu
- Assignee: REALTEK SEMICONDUCTOR CORP.
- Current Assignee: REALTEK SEMICONDUCTOR CORP.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Priority: TW097118127A 20080516
- Main IPC: H01L27/02
- IPC: H01L27/02

Abstract:
A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.
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