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    Method for pairing hosts and I/O peripherals in centralized computer system
    1.
    发明申请
    Method for pairing hosts and I/O peripherals in centralized computer system 审中-公开
    在集中式计算机系统中配对主机和I / O外设的方法

    公开(公告)号：US20080065790A1

    公开(公告)日：2008-03-13

    申请号：US11804421

    申请日：2007-05-17

    Applicant: Chin Tsai Yen ,  Chih Feng Mai ,  Pi-Cheng Chen ,  Te Hsien Lai

    Inventor： Chin Tsai Yen ,  Chih Feng Mai ,  Pi-Cheng Chen ,  Te Hsien Lai

    IPC: G06F3/00

    CPC classification number: H04L61/1523 ,  H04L41/0806 ,  H04L41/0886

    Abstract: The invention discloses a centralized computer system, i.e., so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts and a plurality of I/O peripherals. In particularly, the centralized computer system according to the invention is capable of pairing the hosts and the I/O peripherals.

    Abstract translation: 本发明公开了一种集中式计算机系统，即所谓的刀片PC系统。 根据本发明的集中式计算机系统包括多个集中式和刀片式主机以及多个I / O外围设备。 特别地，根据本发明的集中式计算机系统能够配置主机和I / O外围设备。

    Method and system of characterization and behavioral modeling of a phase-locked loop for fast mixed signal simulation
    2.
    发明授权
    Method and system of characterization and behavioral modeling of a phase-locked loop for fast mixed signal simulation 有权
    用于快速混合信号模拟的锁相环的表征和行为建模方法和系统

    公开(公告)号：US06657500B1

    公开(公告)日：2003-12-02

    申请号：US10042076

    申请日：2002-01-08

    Applicant: Pi-Cheng Chen

    Inventor： Pi-Cheng Chen

    IPC: H03L700

    CPC classification number: G06F17/5036 ,  H03L7/0991

    Abstract: A piecewise linear phase locked loop frequency generator generates a voltage signal controlled by an input voltage. This frequency generator has a variable static frequency generator, whose frequency is selected by a control voltage and whose transfer function between control voltage and output frequency is further selected by a piecewise linear determination parameter. The piecewise linear determination parameter is the number which selects which portion of the frequency spectrum is being represented by the control voltage to frequency transfer function being selected and is a function of an input control voltage. The frequency generator has a set of n low pass filters, used to work in conjunction with the corresponding control voltage to provide frequency transfer functions which are selected by the piecewise linear determination parameter. Finally, a switch circuit is employed to select as a function of the piecewise linear determination parameter which low pass filter output should be presented as the dynamic frequency which corresponds to the original control voltage input. In addition, it is also an objective of this invention to provide a model of a phase locked loop to be simulated within a simulator to determine the function of a phase locked loop within an electronic system.

    Abstract translation: 分段线性锁相环频率发生器产生由输入电压控制的电压信号。 该频率发生器具有可变的静态频率发生器，其频率由控制电压选择，并且通过分段线性确定参数进一步选择控制电压和输出频率之间的传递函数。 分段线性确定参数是选择频谱的哪个部分由选择的频率传递函数的控制电压表示的数量，并且是输入控制电压的函数。 频率发生器具有一组n个低通滤波器，用于与相应的控制电压一起工作，以提供通过分段线性确定参数选择的频率传递函数。 最后，采用开关电路作为分段线性确定参数的函数来选择低通滤波器输出应当作为对应于原始控制电压输入的动态频率。 此外，本发明的目的还在于提供一种在模拟器内仿真以确定电子系统内的锁相环的功能的锁相环的模型。

    Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set
    3.
    发明授权
    Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set 有权

    公开(公告)号：US09443838B2

    公开(公告)日：2016-09-13

    申请号：US12454283

    申请日：2009-05-15

    Applicant: Li-Ping Yang ,  Pi-Cheng Chen ,  Han-Chang Kang ,  Ran-Hong Yan

    Inventor： Li-Ping Yang ,  Pi-Cheng Chen ,  Han-Chang Kang ,  Ran-Hong Yan

    IPC: H01L27/02

    CPC classification number: H01L27/0207 ,  G03F1/00 ,  G03F1/50

    Abstract: A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.

    Method for operating host in hot key way in centralized computer system
    4.
    发明申请
    Method for operating host in hot key way in centralized computer system 审中-公开
    在集中式计算机系统中以热键方式操作主机的方法

    公开(公告)号：US20080065787A1

    公开(公告)日：2008-03-13

    申请号：US11878396

    申请日：2007-07-24

    Applicant: Te-Hsien Lai ,  Pi-Cheng Chen ,  Ming-Chien Yang

    Inventor： Te-Hsien Lai ,  Pi-Cheng Chen ,  Ming-Chien Yang

    IPC: G06F3/01

    CPC classification number: G06F3/023

    Abstract: The invention is to provide a centralized computer system, i.e., so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts. In particularly, the centralized computer system according to the invention enables a set of I/O peripherals to operate a host or a host switch connecting with the host to execute specific functions in a hot key way.

    Abstract translation: 本发明是提供一种集中的计算机系统，即所谓的刀片PC系统。 根据本发明的集中式计算机系统包括多个集中式和刀片式主机。 特别地，根据本发明的集中式计算机系统使一组I / O外围设备能够操作与主机连接的主机或主机交换机，以热键方式执行特定功能。

    Method for cell modeling and timing verification of chip designs with voltage drop
    6.
    发明授权
    Method for cell modeling and timing verification of chip designs with voltage drop 有权
    具有电压降的芯片设计的电池建模和定时验证方法

    公开(公告)号：US06453443B1

    公开(公告)日：2002-09-17

    申请号：US09835028

    申请日：2001-04-16

    Applicant: Pi-Cheng Chen ,  Wen-Hao Chen ,  Ming-Chyuan Chen ,  Hsien-Te Chen

    Inventor： Pi-Cheng Chen ,  Wen-Hao Chen ,  Ming-Chyuan Chen ,  Hsien-Te Chen

    IPC: G06F1750

    CPC classification number: G06F17/5022

    Abstract: In the present invention a method is described to produce a whole chip timing verification that includes the effects of voltage variation on delay. This is done by creating a netlist, defining cell input and output (I/O) delay paths, and calculating the difference timing caused by differences in power supply voltage. The incremental I/O path delay is calculated by adding delay changes caused by all power pins. Whole chip timings are generated without consideration to voltage drops and then modified using the incremental path delay. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification.

    Abstract translation: 在本发明中，描述了一种方法来产生包括电压变化对延迟的影响的整个芯片定时验证。 这通过创建网表，定义单元输入和输出（I / O）延迟路径以及计算由电源电压差异引起的差异定时来完成。 通过增加由所有电源引脚引起的延迟更改来计算增量I / O路径延迟。 在不考虑电压降的情况下生成整个芯片定时，然后使用增量路径延迟进行修改。 经修改的全芯片定时数据文件与传统的定时验证工具一起使用，以执行整个芯片单元级定时验证。

    Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set
    8.
    发明申请
    Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set 有权
    集成电路制造方法，集成电路元件掩模布局集和分量光掩模集

    公开(公告)号：US20090286358A1

    公开(公告)日：2009-11-19

    申请号：US12454283

    申请日：2009-05-15

    Applicant: Li-Ping Yang ,  Pi-Cheng Chen ,  Han-Chang Kang ,  Ran-Hong Yan

    Inventor： Li-Ping Yang ,  Pi-Cheng Chen ,  Han-Chang Kang ,  Ran-Hong Yan

    IPC: H01L21/50 ,  H01L21/304 ,  G06F17/50 ,  G03F1/00

    CPC classification number: H01L27/0207 ,  G03F1/00 ,  G03F1/50

    Abstract: A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.

    Abstract translation: 一种制造集成电路的方法包括以下步骤：a）参考硬件单元的物理设计，准备与适用于在晶片上制造硬件单元的阵列的分量光掩模相关联的集成电路部件掩模布局集合; b）参考集成电路元件掩模布局集合准备分量光掩模; c）使用在步骤b）中制备的分量光掩模，在晶片上的相邻硬件单元之间形成硬件单元的阵列和互连; 以及d）沿选定的划线切割晶片，以形成多个集成电路管芯。 每个集成电路管芯独立地从仅包括一个硬件单元的单一类型中选择，并且包括通过未切割的导电路径电连接的多个硬件单元的多种类型。

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