Invention Grant
- Patent Title: Fabricating stacked nanowire, field-effect transistors
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Application No.: US14988050Application Date: 2016-01-05
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Publication No.: US09443931B2Publication Date: 2016-09-13
- Inventor: Hui Zang , Guillaume Bouche , Gabriel Padron Wells
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley and Mesiti PC
- Agent Nicholas Mesiti
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L27/12 ; H01L31/0392 ; H01L29/06 ; H01L29/66 ; H01L29/161 ; H01L29/16 ; H01L21/311 ; H01L21/308 ; H01L29/78

Abstract:
Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).
Public/Granted literature
- US20160155800A1 FABRICATING STACKED NANOWIRE, FIELD-EFFECT TRANSISTORS Public/Granted day:2016-06-02
Information query
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