Invention Grant
- Patent Title: Three dimensional memory array architecture
- Patent Title (中): 三维内存阵列架构
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Application No.: US14268649Application Date: 2014-05-02
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Publication No.: US09444046B2Publication Date: 2016-09-13
- Inventor: Federico Pio
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L45/00
- IPC: H01L45/00 ; G11C11/00 ; H01L47/00 ; H01L21/283 ; H01L29/82 ; H01L27/10 ; H01L27/24 ; H01L29/417 ; H01L29/78 ; H01L27/06

Abstract:
Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.
Public/Granted literature
- US20140295638A1 THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE Public/Granted day:2014-10-02
Information query
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