Disclosed is a synchronous DC-DC converter including: a clock signal generator which generates a clock signal; a gate driving part which is connected to the clock signal generator and outputs a first delay clock signal and a second delay clock signal with respect to the clock signal; a switching part which is connected to the gate driving part and includes a first switching element and a second switching element which are complementarily switched according to each of the first delay clock signal and the second delay clock signal; and a controller which is connected to the switching part and generates a control signal which is usable by the gate driving part in order to control a dead time between the first switching element and the second switching element.