Invention Grant
US09448284B2 Method and apparatus for test time reduction using fractional data packing
有权
使用分数据包装的测试时间缩短的方法和装置
- Patent Title: Method and apparatus for test time reduction using fractional data packing
- Patent Title (中): 使用分数据包装的测试时间缩短的方法和装置
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Application No.: US14272760Application Date: 2014-05-08
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Publication No.: US09448284B2Publication Date: 2016-09-20
- Inventor: Sreenath Narayanan Potty , Rajesh Mittal , Mudasir Shafat Kawoosa , Vivek Singhal
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/3183
- IPC: G01R31/3183 ; G01R31/3185 ; G01R31/317 ; G01R31/3177

Abstract:
An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.
Public/Granted literature
- US20150323596A1 METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA PACKING Public/Granted day:2015-11-12
Information query
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