Invention Grant
- Patent Title: Inter-chip memory interface structure
- Patent Title (中): 片内存储接口结构
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Application No.: US13752427Application Date: 2013-01-29
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Publication No.: US09448947B2Publication Date: 2016-09-20
- Inventor: Jungwon Suh , Dexter T. Chun
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Kenneth K. Vu; Paul Holdaway
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G11C5/04 ; G11C5/06 ; G11C7/02 ; G11C7/22 ; H01L25/065 ; H01L25/10

Abstract:
In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.
Public/Granted literature
- US20130326188A1 INTER-CHIP MEMORY INTERFACE STRUCTURE Public/Granted day:2013-12-05
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