发明授权
US09450073B2 SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto
有权
SOI晶体管具有减小长度的漏极和源极区域以及与其相邻的应力介电材料
- 专利标题： SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto
- 专利标题（中）： SOI晶体管具有减小长度的漏极和源极区域以及与其相邻的应力介电材料
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申请号： US11936855申请日： 2007-11-08
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公开(公告)号： US09450073B2公开(公告)日： 2016-09-20
- 发明人: Andy Wei , Thorsten Kammler , Roman Boschke , Casey Scott
- 申请人： Andy Wei , Thorsten Kammler , Roman Boschke , Casey Scott
- 申请人地址： US CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 优先权： DE102007015504 20070330
- 主分类号： H01L27/12
- IPC分类号： H01L27/12 ; H01L29/66 ; H01L29/78 ; H01L21/762 ; H01L21/84 ; H01L29/417 ; H01L29/786
摘要：
By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.
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