公开(公告)号：US20080182371A1

公开(公告)日：2008-07-31

申请号：US11778930

申请日：2007-07-17

申请人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L21/8238

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

摘要： By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

摘要翻译： 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US09450073B2

公开(公告)日：2016-09-20

申请号：US11936855

申请日：2007-11-08

申请人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/6659 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

摘要翻译： 通过在SOI晶体管的漏极和源极区域中形成的凹槽中重新配置材料，在形成相应的金属硅化物区域之前，可以将凹槽的深度增加到掩埋绝缘层，从而当对应的金属硅化物区域时减小串联电阻并增强应力传递 晶体管元件被高应力介电材料覆盖。 材料再分配可以基于高温氢气烘烤来实现。

公开(公告)号：US20080237712A1

公开(公告)日：2008-10-02

申请号：US11936855

申请日：2007-11-08

申请人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

摘要翻译： 通过在SOI晶体管的漏极和源极区域中形成的凹槽中重新配置材料，在形成相应的金属硅化物区域之前，可以将凹槽的深度增加到掩埋绝缘层，从而当对应的金属硅化物区域时减小串联电阻并增强应力传递 晶体管元件被高应力介电材料覆盖。 材料再分配可以基于高温氢气烘烤来实现。

公开(公告)号：US08652913B2

公开(公告)日：2014-02-18

申请号：US11778930

申请日：2007-07-17

申请人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

摘要： By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

摘要翻译： 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US07763515B2

公开(公告)日：2010-07-27

申请号：US11843358

申请日：2007-08-22

申请人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Manfred Horstmann

IPC分类号： H01L21/8234

CPC分类号： H01L29/66636 ,  H01L21/76256 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78684 ,  Y10S438/938

摘要： By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According to one embodiment of the invention, the lattice mismatch may be adapted by a biaxial strain in the first semiconductor material. According to one embodiment, the lattice mismatch may be adjusted by a biaxial strain in the first semiconductor material. In particular, the strain transfer of strain sources including the embedded second semiconductor material as well as a strained overlayer is increased. According to one illustrative embodiment, regions of different biaxial strain may be provided for different transistor types.

摘要翻译： 通过组合沟道区中的第一半导体材料和晶体管的源极/漏极区域中嵌入的第二半导体材料之间的分别适配的晶格失配，进入沟道区的应变增加。 根据本发明的一个实施例，晶格失配可以通过第一半导体材料中的双轴应变来适应。 根据一个实施例，可以通过第一半导体材料中的双轴应变来调整晶格失配。 特别地，包括嵌入的第二半导体材料以及应变覆盖层的应变源的应变传递增加。 根据一个说明性实施例，可以为不同的晶体管类型提供不同双轴应变的区域。

公开(公告)号：US20080179628A1

公开(公告)日：2008-07-31

申请号：US11843358

申请日：2007-08-22

申请人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Manfred Horstmann

IPC分类号： H01L29/778 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/76256 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78684 ,  Y10S438/938

摘要： By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According to one embodiment of the invention, the lattice mismatch may be adapted by a biaxial strain in the first semiconductor material. According to one embodiment, the lattice mismatch may be adjusted by a biaxial strain in the first semiconductor material. In particular, the strain transfer of strain sources including the embedded second semiconductor material as well as a strained overlayer is increased. According to one illustrative embodiment, regions of different biaxial strain may be provided for different transistor types.

摘要翻译： 通过组合沟道区中的第一半导体材料和晶体管的源极/漏极区域中嵌入的第二半导体材料之间的分别适配的晶格失配，进入沟道区的应变增加。 根据本发明的一个实施例，晶格失配可以通过第一半导体材料中的双轴应变来适应。 根据一个实施例，可以通过第一半导体材料中的双轴应变来调整晶格失配。 特别地，包括嵌入的第二半导体材料以及应变覆盖层的应变源的应变传递增加。 根据一个说明性实施例，可以为不同的晶体管类型提供不同双轴应变的区域。

公开(公告)号：US20110024846A1

公开(公告)日：2011-02-03

申请号：US12838810

申请日：2010-07-19

申请人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region.

摘要翻译： 在静态存储单元中，通过在有源区的尖端部分通过隔离侧壁并入注入物质，可以显着地减少形成连接有源区与形成在隔离区上方的栅电极结构的接触元件之间的故障率 在用绝缘材料填充之前，该沟槽。 注入物质可以表示P型掺杂物种类和/或惰性物质，用于显着改变活性区的末端部分的材料特性。

公开(公告)号：US08481404B2

公开(公告)日：2013-07-09

申请号：US12838810

申请日：2010-07-19

申请人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L21/76

CPC分类号： H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region.

摘要翻译： 在静态存储单元中，通过在有源区的尖端部分通过隔离侧壁并入注入物质，可以显着地减少形成连接有源区与形成在隔离区上方的栅电极结构的接触元件之间的故障率 在用绝缘材料填充之前，该沟槽。 注入物质可以表示P型掺杂物种类和/或惰性物质，用于显着改变活性区的末端部分的材料特性。

公开(公告)号：US07659213B2

公开(公告)日：2010-02-09

申请号：US11566840

申请日：2006-12-05

申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC分类号： H01L21/31 ,  H01L21/42 ,  H01L21/8222

CPC分类号： C23C8/20 ,  C23C8/80 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.

摘要翻译： 通过离子注入和随后的基于闪光或基于激光的退火工艺引入碳，具有拉伸应变的应变硅/碳材料可以紧邻通道区域定位，从而增强应变诱导机制。 可以在碳注入之前进行预非晶化注入，例如基于硅。 此外，通过去除用于形成深漏极和源极区的间隔结构，应变硅/碳材料相对于栅极的横向偏移程度可以基本上独立于其它工艺要求来确定。 此外，用于形成金属硅化物区域的附加侧壁间隔物可以具有降低的介电常数，从而另外有助于整体性能提高。

公开(公告)号：US20090321836A1

公开(公告)日：2009-12-31

申请号：US12473610

申请日：2009-05-28

申请人： Andy Wei ,  Robert Mulfinger ,  Thilo Scheiper ,  Thorsten Kammler

发明人： Andy Wei ,  Robert Mulfinger ,  Thilo Scheiper ,  Thorsten Kammler

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

摘要： Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

摘要翻译： 可以基于增强的掩模状态形成诸如FinFETS和三栅极晶体管的三维晶体管结构，从而能够在体半导体内以自对准的方式形成漏极和源极区域，鳍片和隔离结构 材料。 在定义基本的翅片结构之后，可以使用平面晶体管配置的高效制造技术，从而进一步提高三维晶体管配置的整体性能。