Invention Grant
- Patent Title: System and method of varying gate lengths of multiple cores
- Patent Title (中): 不同核心长度不同的系统和方法
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Application No.: US14792363Application Date: 2015-07-06
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Publication No.: US09461040B2Publication Date: 2016-10-04
- Inventor: Ming Cai , Samit Sengupta , Chock Hing Gan , PR Chidambaram
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Toler Law Group, PC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/66 ; H01L27/00 ; H01L29/00 ; G06F17/50 ; H01L27/088 ; H01L29/49 ; H01L21/28 ; H01L21/8234 ; H01L27/02
Abstract:
A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.
Public/Granted literature
- US20150311198A1 SYSTEM AND METHOD OF VARYING GATE LENGTHS OF MULTIPLE CORES Public/Granted day:2015-10-29
Information query
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