Invention Grant
- Patent Title: Non-planar III-N transistor
- Patent Title (中): 非平面III-N晶体管
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Application No.: US13976837Application Date: 2011-12-19
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Publication No.: US09461160B2Publication Date: 2016-10-04
- Inventor: Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
- Applicant: Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/065922 WO 20111219
- International Announcement: WO2013/095346 WO 20130627
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/66 ; H01L29/78 ; H01L29/20

Abstract:
Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.
Public/Granted literature
- US20130277683A1 NON-PLANAR III-N TRANSISTOR Public/Granted day:2013-10-24
Information query
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