Invention Grant
US09466715B2 MOS transistor having a gate dielectric with multiple thicknesses
有权
MOS晶体管具有多个厚度的栅极电介质
- Patent Title: MOS transistor having a gate dielectric with multiple thicknesses
- Patent Title (中): MOS晶体管具有多个厚度的栅极电介质
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Application No.: US14015350Application Date: 2013-08-30
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Publication No.: US09466715B2Publication Date: 2016-10-11
- Inventor: Chih-Chang Cheng , Fu-Yu Chu , Ruey-Hsin Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/51 ; H01L29/423 ; H01L29/66 ; H01L21/8234 ; H01L21/336 ; H01L21/02

Abstract:
A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.
Public/Granted literature
- US20150061011A1 MOS TRANSISTOR Public/Granted day:2015-03-05
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