Invention Grant
US09471091B2 Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled 有权
周期性同步器使用缩短的时序余量来生成被验证或召回的推测同步输出信号

  • Patent Title: Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled
  • Patent Title (中): 周期性同步器使用缩短的时序余量来生成被验证或召回的推测同步输出信号
  • Application No.: US13688170
    Application Date: 2012-11-28
  • Publication No.: US09471091B2
    Publication Date: 2016-10-18
  • Inventor: William J. DallyStephen G. Tell
  • Applicant: NVIDIA Corporation
  • Applicant Address: US CA Santa Clara
  • Assignee: NVIDIA Corporation
  • Current Assignee: NVIDIA Corporation
  • Current Assignee Address: US CA Santa Clara
  • Agency: Zilka-Kotab, PC
  • Main IPC: G06F1/24
  • IPC: G06F1/24 G06F1/12
Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled
Abstract:
A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.
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