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公开(公告)号：US20240311626A1
公开(公告)日：2024-09-19
申请号：US18674632
申请日：2024-05-24
Applicant: NVIDIA Corporation
Abstract: Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.
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公开(公告)号：US20140139275A1
公开(公告)日：2014-05-22
申请号：US13681929
申请日：2012-11-20
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally , Stephen G. Tell
IPC: H03L7/00
Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.
Abstract translation: 提供了用于变形容限同步的方法和系统。 接收表示相对于第一时钟信号的第二时钟信号的相位和表示第二时钟信号和第一时钟信号之间的相对周期的周期值的相位值。 基于相位值和周期值计算第二时钟信号相对于与第一时钟信号的下一个转换相对应的第一时钟信号的外推相位值。
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公开(公告)号：US12191868B2
公开(公告)日：2025-01-07
申请号：US18595042
申请日：2024-03-04
Applicant: NVIDIA Corporation
Inventor： Sanquan Song , Stephen G. Tell , Nikola Nedovic
Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.
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公开(公告)号：US20210056399A1
公开(公告)日：2021-02-25
申请号：US16750917
申请日：2020-01-23
Applicant: NVIDIA Corporation
Abstract: Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.
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公开(公告)号：US20140321579A1
公开(公告)日：2014-10-30
申请号：US13870921
申请日：2013-04-25
Applicant: NVIDIA CORPORATION
Inventor： Stephen G. Tell , John W. Poulton
IPC: H04B1/30
CPC classification number: H04L25/063
Abstract: A system and method are provided for tuning a serial link. The method includes receiving, by a receiver circuit, an offset correction pattern transmitted over a serial link and sampling the received offset correction pattern based on an offset correction parameter to generate a sampled signal. A distribution of the sampled signal is computed and the offset correction parameter is set based on the distribution. The system includes a receiver circuit that is coupled to the serial link and an offset correction unit that is coupled to the receiver circuit. The receiver circuit is configured to receive the offset correction pattern and sample the received offset correction pattern based on the offset correction parameter to generate the sampled signal. The offset correction unit is configured to compute the distribution of the sampled signal and set the offset correction parameter based on the distribution.
Abstract translation: 提供了一种用于调节串行链路的系统和方法。 该方法包括由接收器电路接收通过串行链路发送的偏移校正模式，并且基于偏移校正参数对接收到的偏移校正模式进行采样以产生采样信号。 计算采样信号的分布，并根据分布设置偏移校正参数。 该系统包括耦合到串行链路的接收机电路和耦合到接收机电路的偏移校正单元。 接收器电路被配置为接收偏移校正图案并且基于偏移校正参数对接收到的偏移校正图案进行采样以产生采样信号。 偏移校正单元被配置为计算采样信号的分布，并且基于分布设置偏移校正参数。
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Patent Agency Ranking
公开(公告)号：US08760204B2
公开(公告)日：2014-06-24
申请号：US13681929
申请日：2012-11-20
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Stephen G. Tell
IPC: H03L7/00
Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.
Abstract translation: 提供了用于变形容限同步的方法和系统。 接收表示相对于第一时钟信号的第二时钟信号的相位和表示第二时钟信号和第一时钟信号之间的相对周期的周期值的相位值。 基于相位值和周期值计算第二时钟信号相对于与第一时钟信号的下一个转换相对应的第一时钟信号的外推相位值。
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公开(公告)号：US20240204785A1
公开(公告)日：2024-06-20
申请号：US18595042
申请日：2024-03-04
Applicant: NVIDIA Corporation
Inventor： Sanquan Song , Stephen G. Tell , Nikola Nedovic
CPC classification number: H03L7/099 , H03L7/0891
Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.
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8.发明授权Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled 有权周期性同步器使用缩短的时序余量来生成被验证或召回的推测同步输出信号公开(公告)号：US09471091B2
公开(公告)日：2016-10-18
申请号：US13688170
申请日：2012-11-28
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Stephen G. Tell
CPC classification number: G06F1/12
Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.
Abstract translation: 提供了一种用于推测周期性同步的方法和系统。 接收表示相对于在至少一个周期测量的第一时钟信号的第二时钟信号的测量相位的相位值。 还接收表示相对于先前测量的至少一个周期的第一时钟信号的第二时钟信号的周期的周期值。 基于相位值和周期值确定缩短的定时裕度。 基于减小的时序余量产生推测同步的输出信号。
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公开(公告)号：US09164134B2
公开(公告)日：2015-10-20
申请号：US13676021
申请日：2012-11-13
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Stephen G. Tell
CPC classification number: G01R25/00
Abstract: A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.
Abstract translation: 提供了一种用于时钟相位检测的方法和系统。 产生一组第一时钟信号的延迟版本。 第一时钟的延迟版本集用于采样第二时钟信号，产生与第一时钟信号相对应的域中的采样序列。 至少一个边缘指示位于样本序列内。
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公开(公告)号：US09100094B2
公开(公告)日：2015-08-04
申请号：US13870921
申请日：2013-04-25
Applicant: NVIDIA Corporation
Inventor： Stephen G. Tell , John W. Poulton
IPC: H04B1/30
CPC classification number: H04L25/063
Abstract: A system and method are provided for tuning a serial link. The method includes receiving, by a receiver circuit, an offset correction pattern transmitted over a serial link and sampling the received offset correction pattern based on an offset correction parameter to generate a sampled signal. A distribution of the sampled signal is computed and the offset correction parameter is set based on the distribution. The system includes a receiver circuit that is coupled to the serial link and an offset correction unit that is coupled to the receiver circuit. The receiver circuit is configured to receive the offset correction pattern and sample the received offset correction pattern based on the offset correction parameter to generate the sampled signal. The offset correction unit is configured to compute the distribution of the sampled signal and set the offset correction parameter based on the distribution.
Abstract translation: 提供了一种用于调节串行链路的系统和方法。 该方法包括由接收器电路接收通过串行链路发送的偏移校正模式，并且基于偏移校正参数对接收到的偏移校正模式进行采样以产生采样信号。 计算采样信号的分布，并根据分布设置偏移校正参数。 该系统包括耦合到串行链路的接收机电路和耦合到接收机电路的偏移校正单元。 接收器电路被配置为接收偏移校正图案并且基于偏移校正参数对接收到的偏移校正图案进行采样以产生采样信号。 偏移校正单元被配置为计算采样信号的分布，并且基于分布设置偏移校正参数。
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