Invention Grant
US09471501B2 Hardware apparatuses and methods to control access to a multiple bank data cache
有权
用于控制对多组数据高速缓存的访问的硬件设备和方法
- Patent Title: Hardware apparatuses and methods to control access to a multiple bank data cache
- Patent Title (中): 用于控制对多组数据高速缓存的访问的硬件设备和方法
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Application No.: US14498902Application Date: 2014-09-26
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Publication No.: US09471501B2Publication Date: 2016-10-18
- Inventor: Andrey Kluchnikov , Jayesh Iyer , Sergey Y. Shishlov , Boris A. Babayan
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Webster & Elliott, LLP
- Agent Nicholson De Vos
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F13/18

Abstract:
Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
Public/Granted literature
- US20160092367A1 HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BANK DATA CACHE Public/Granted day:2016-03-31
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