Invention Grant
- Patent Title: Semiconductor structure with inlaid capping layer and method of manufacturing the same
- Patent Title (中): 具有镶嵌层的半导体结构及其制造方法
-
Application No.: US14155682Application Date: 2014-01-15
-
Publication No.: US09472449B2Publication Date: 2016-10-18
- Inventor: Kuan-Chia Chen , Shing-Chyang Pan , Chih-Chien Chi , Ching-Hua Hsieh
- Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/532

Abstract:
A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.
Public/Granted literature
- US20150200126A1 Semiconductor Structure With Inlaid Capping Layer And Method Of Manufacturing The Same Public/Granted day:2015-07-16
Information query
IPC分类: