Invention Grant
- Patent Title: Back gate in select transistor for eDRAM
- Patent Title (中): eDRAM选择晶体管的背栅
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Application No.: US14761471Application Date: 2013-12-12
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Publication No.: US09472469B2Publication Date: 2016-10-18
- Inventor: Gerhard Enders , Franz Hofmann
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agent Jeffrey T. Holman
- Priority: FR1350547 20130122
- International Application: PCT/EP2013/076414 WO 20131212
- International Announcement: WO2014/114406 WO 20140731
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84 ; H01L29/786 ; H01L27/108
Abstract:
This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.
Public/Granted literature
- US20150357333A1 BACK GATE IN SELECT TRANSISTOR FOR EDRAM Public/Granted day:2015-12-10
Information query
IPC分类:
