公开(公告)号：US09640664B2

公开(公告)日：2017-05-02

申请号：US14428561

申请日：2013-09-10

Applicant: Soitec

Inventor： Franz Hofmann

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L27/0214 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7855

Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.

公开(公告)号：US20150171094A1

公开(公告)日：2015-06-18

申请号：US14413405

申请日：2013-07-04

Applicant: Soitec

Inventor： Franz Hofmann

IPC: H01L27/112

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/11286 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

Abstract translation: 本公开涉及一种半导体结构，包括：第一半导体层，第一编程晶体管和实现第一反熔丝电池的第一选择晶体管，其中第一半导体层用作第一编程晶体管的主体，并且作为第一半导体的主体 第一选择晶体管，其中第一编程晶体管的栅极和第一选择晶体管的栅极位于第一半导体层的不同侧。

公开(公告)号：US20150357333A1

公开(公告)日：2015-12-10

申请号：US14761471

申请日：2013-12-12

Applicant: SOITEC

Inventor： Gerhard Enders ,  Franz Hofmann

IPC: H01L27/108 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/78648

Abstract: This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.

Abstract translation: 本公开涉及一种eDRAM存储元件，其包括第一存储节点，用于访问存储在存储节点中的值的位线节点和控制从位线节点到存储节点的访问的选择晶体管，其中选择晶体管具有前端 门和后门。

公开(公告)号：US10186515B2

公开(公告)日：2019-01-22

申请号：US14413405

申请日：2013-07-04

Applicant: Soitec

Inventor： Franz Hofmann

IPC: H01L27/11 ,  H01L21/70 ,  H01L27/112 ,  G11C17/16 ,  H01L27/10 ,  H01L27/12 ,  H01L23/525

Abstract: The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

公开(公告)号：US09472469B2

公开(公告)日：2016-10-18

申请号：US14761471

申请日：2013-12-12

Applicant: Soitec

Inventor： Gerhard Enders ,  Franz Hofmann

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/786 ,  H01L27/108

CPC classification number: H01L21/84 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/78648

Abstract: This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.

Abstract translation: 本公开涉及一种eDRAM存储元件，其包括第一存储节点，用于访问存储在存储节点中的值的位线节点和控制从位线节点到存储节点的访问的选择晶体管，其中选择晶体管具有前端 门和后门。

公开(公告)号：US20150214372A1

公开(公告)日：2015-07-30

申请号：US14428561

申请日：2013-09-10

Applicant: SOITEC

Inventor： Franz Hofmann

IPC: H01L29/78 ,  H01L27/12 ,  H01L27/02 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L27/0214 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7855

Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.

Abstract translation: 本发明涉及一种用于使至少第一鳍式晶体管和第二鳍式晶体管偏振的方法，其中所述第一鳍式晶体管具有比所述第二鳍式晶体管的鳍宽大的鳍宽度，以及所述第一鳍鳍晶体管和所述第二鳍鳍晶体管 finfet晶体管具有背栅，并且该方法包括在第一finfet晶体管的背栅极和第二finfet晶体管的背栅上施加相同的第一电压，以便减小第一finfet晶体管的截止电流值 finfet晶体管和第二finfet晶体管的截止电流值。