Invention Grant
US09472667B2 III-V MOSFET with strained channel and semi-insulating bottom barrier
有权
具有应变通道和半绝缘底部屏障的III-V MOSFET
- Patent Title: III-V MOSFET with strained channel and semi-insulating bottom barrier
- Patent Title (中): 具有应变通道和半绝缘底部屏障的III-V MOSFET
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Application No.: US14592130Application Date: 2015-01-08
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Publication No.: US09472667B2Publication Date: 2016-10-18
- Inventor: Anirban Basu , Guy Cohen , Amlan Majumdar
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Edward J. Wixted, III
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/78 ; H01L29/66 ; H01L29/20

Abstract:
Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.
Public/Granted literature
- US20160204253A1 III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER Public/Granted day:2016-07-14
Information query
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