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公开(公告)号：US10559666B2
公开(公告)日：2020-02-11
申请号：US16247989
申请日：2019-01-15
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/205 , H01L21/762 , H01L21/02
摘要： A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.
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公开(公告)号：US09985113B2
公开(公告)日：2018-05-29
申请号：US15426566
申请日：2017-02-07
发明人： Anirban Basu , Guy Cohen , Amlan Majumdar
IPC分类号： H01L29/66 , H01L29/78 , H01L29/08 , H01L29/201 , H01L29/205
CPC分类号： H01L29/66636 , H01L29/0847 , H01L29/201 , H01L29/205 , H01L29/66522 , H01L29/66795 , H01L29/7784 , H01L29/785 , H01L29/7851
摘要： A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.
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公开(公告)号：US20180130885A1
公开(公告)日：2018-05-10
申请号：US15797852
申请日：2017-10-30
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/205 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02
CPC分类号： H01L29/205 , H01L21/02241 , H01L21/762 , H01L29/66795 , H01L29/785
摘要： A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.
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公开(公告)号：US09773903B2
公开(公告)日：2017-09-26
申请号：US15377722
申请日：2016-12-13
发明人： Cheng-Wei Cheng , Pranita Kerber , Effendi Leobandung , Amlan Majumdar , Renee T. Mo , Yanning Sun
IPC分类号： H01L29/78 , H01L23/535 , H01L29/06 , H01L29/32 , H01L29/66 , H01L21/311 , H01L29/778
CPC分类号： H01L29/7835 , H01L21/2258 , H01L21/31105 , H01L21/31116 , H01L23/535 , H01L29/0649 , H01L29/1054 , H01L29/32 , H01L29/66462 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.
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公开(公告)号：US09748357B2
公开(公告)日：2017-08-29
申请号：US15229198
申请日：2016-08-05
发明人： Anirban Basu , Guy Cohen , Amlan Majumdar
CPC分类号： H01L29/66522 , H01L29/0649 , H01L29/1033 , H01L29/1054 , H01L29/1079 , H01L29/20 , H01L29/7842 , H01L29/7849
摘要： Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.
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6.发明授权Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels 有权通过低有效质量通道减少场效应晶体管中的直接源极到漏极隧穿公开(公告)号：US09564514B2
公开(公告)日：2017-02-07
申请号：US14931930
申请日：2015-11-04
发明人： Anirban Basu , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L29/88 , H01L21/329 , H01L21/336 , H01L29/74 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/20 , H01L29/417 , H01L29/423 , H01L29/786 , H01L29/165 , H01L29/205
CPC分类号： H01L29/66666 , H01L29/0603 , H01L29/1037 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/41741 , H01L29/41775 , H01L29/42392 , H01L29/66522 , H01L29/66553 , H01L29/6656 , H01L29/7827 , H01L29/78609 , H01L29/78642 , H01L29/78681 , H01L29/78696
摘要： An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
摘要翻译： 在具有低有效质量通道材料的垂直场效应晶体管中提供势垒的方法，其中所述势垒的形成包括在半导体衬底上形成第一源极/漏极接触并且在所述第一源极/漏极上形成具有第一沟道层的沟道， 排水接触。 该方法还包括在第一沟道层上形成势垒，在栅极上形成第二沟道层，然后在第二沟道层上形成第二源极/漏极接触。
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公开(公告)号：US09553166B1
公开(公告)日：2017-01-24
申请号：US14841033
申请日：2015-08-31
发明人： Cheng-Wei Cheng , Pranita Kerber , Effendi Leobandung , Amlan Majumdar , Renee T. Mo , Yanning Sun
IPC分类号： H01L29/66 , H01L29/778 , H01L21/311 , H01L21/225
CPC分类号： H01L29/7835 , H01L21/2258 , H01L21/31105 , H01L21/31116 , H01L23/535 , H01L29/0649 , H01L29/1054 , H01L29/32 , H01L29/66462 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.
摘要翻译： 提供了包含高迁移率半导体沟道材料即III-V族半导体材料的半导体结构以及位于高迁移率半导体沟道材料的侧壁上的非对称源/漏区。 不对称的源极/漏极区域有助于改善所得器件的性能。 源极区域包含源极侧外延掺杂半导体材料，而漏极区域包含漏极侧外延掺杂半导体材料和高迁移率半导体沟道材料的下面部分。
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8.发明授权III-V MOSFET with strained channel and semi-insulating bottom barrier 有权具有应变通道和半绝缘底部屏障的III-V MOSFET公开(公告)号：US09472667B2
公开(公告)日：2016-10-18
申请号：US14592130
申请日：2015-01-08
发明人： Anirban Basu , Guy Cohen , Amlan Majumdar
CPC分类号： H01L29/66522 , H01L29/0649 , H01L29/1033 , H01L29/1054 , H01L29/1079 , H01L29/20 , H01L29/7842 , H01L29/7849
摘要： Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.
摘要翻译： 实施例包括一种用于制造半导体器件的方法，并且所得结构包括在半导体衬底上形成半绝缘底部势垒。 在底部屏障上形成通道。 半绝缘层外延地形成在底部屏障上，横向邻近通道。 半绝缘层以使得在沟道上产生应力的方式形成。 在沟道上形成CMOS晶体管。
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公开(公告)号：US20160181394A1
公开(公告)日：2016-06-23
申请号：US14578768
申请日：2014-12-22
CPC分类号： H01L29/66522 , H01L29/1083 , H01L29/205 , H01L29/66492 , H01L29/66537 , H01L29/66575 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7834
摘要： Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.
摘要翻译： 提供了通过使用卤素掺杂的底部（III-V）阻挡层来控制III-V MOSFET中的短沟道效应的技术。 在一个方面，提供了一种形成MOSFET器件的方法。 该方法包括以下步骤：在衬底上形成III-V阻挡层; 在与衬底相对的III-V阻挡层的一侧上形成III-V沟道层，其中III-V势垒层被配置为将MOSFET器件中的电荷载流子限制到III-V沟道层; 在与III-V阻挡层相对的III-V沟道层的一侧上形成栅叠层; 以及在栅堆叠的相对侧上的III-V阻挡层中形成晕轮植入物。 还提供MOSFET器件。
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10.发明申请REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS 有权在低效率质量通道的场效应晶体管中减少直接源到漏电隧道公开(公告)号：US20160149050A1
公开(公告)日：2016-05-26
申请号：US14931930
申请日：2015-11-04
发明人： Anirban Basu , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L29/423
CPC分类号： H01L29/66666 , H01L29/0603 , H01L29/1037 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/41741 , H01L29/41775 , H01L29/42392 , H01L29/66522 , H01L29/66553 , H01L29/6656 , H01L29/7827 , H01L29/78609 , H01L29/78642 , H01L29/78681 , H01L29/78696
摘要： An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
摘要翻译： 在具有低有效质量通道材料的垂直场效应晶体管中提供势垒的方法，其中所述势垒的形成包括在半导体衬底上形成第一源极/漏极接触并且在所述第一源极/漏极上形成具有第一沟道层的沟道， 排水接触。 该方法还包括在第一沟道层上形成势垒，在栅极上形成第二沟道层，然后在第二沟道层上形成第二源极/漏极接触。
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