Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.