Invention Grant
US09478542B1 Multi-gate device with planar channel 有权
具有平面通道的多栅极器件

Multi-gate device with planar channel
Abstract:
A semiconductor device includes a substrate having a well region implanted with a first dopant by a first well implantation and a non-doped section blocked from the first well implantation. The semiconductor device includes a semiconductor fin formed on the substrate, in which the semiconductor fin has a channel stop region and a channel region above the channel stop region. The channel stop region has a portion of the non-doped section and a portion of the well region. The semiconductor fin has a planar channel formed at an interface between the non-doped section and the channel region for additional current flow between source and drain regions of the semiconductor fin. The semiconductor device includes an isolation layer disposed adjacent to and in contact with the well region and the channel stop region. The semiconductor device also includes a gate structure disposed on the isolation layer and around the channel region.
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