Invention Grant
- Patent Title: Tristate gate
- Patent Title (中): 三口门
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Application No.: US14364923Application Date: 2012-12-11
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Publication No.: US09479174B2Publication Date: 2016-10-25
- Inventor: Richard Ferrant
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: SOITEC
- Current Assignee: SOITEC
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: EP11290575 20111213
- International Application: PCT/EP2012/075054 WO 20121211
- International Announcement: WO2013/087612 WO 20130620
- Main IPC: H03K19/094
- IPC: H03K19/094 ; H01L27/088 ; H01L27/12
Abstract:
A tristate gate includes an output port and at least two transistors. Each of the transistors has at least a first and a second gate configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.
Public/Granted literature
- US20140340118A1 TRISTATE GATE Public/Granted day:2014-11-20
Information query
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