公开(公告)号：US10110235B2

公开(公告)日：2018-10-23

申请号：US14381544

申请日：2013-02-22

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/177 ,  H03K19/003 ,  H03K19/00

Abstract: The present invention relates to a look-up table architecture and to an FPGA comprising the same. The look-up table architecture comprises a registers group comprising a plurality of registers configured to issue register signals, and a programmable logic comprising a plurality of pass gates configured to be controlled at least by the register signals, the registers group and the programmable logic forming a look-up table, wherein the pass gates are placed in a single direction.

公开(公告)号：US09576642B2

公开(公告)日：2017-02-21

申请号：US14785955

申请日：2014-04-24

Applicant: Soitec

Inventor： Roland Thewes ,  Richard Ferrant

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/18 ,  G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/04 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4099

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array,—at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract translation: 本发明涉及一种半导体存储器件，包括：至少一个读出放大器电路，用于读取从存储器阵列中的选定存储单元感测的数据，至少一个参考电路，每个参考电路是读出放大器电路的复制品，并具有输出 参考电路通过其输出输出物理量;调节网络，向每个读出放大器电路和每个参考电路提供调节信号，其中调节信号是根据输出物理量随时间和/或空间的平均得出的，其中 调节网络包括：控制单元，被配置为将参考电路的每个输出的物理量与目标平均值相加，所述控制单元基于所述和传送调节信号，所述调节信号馈送到每个常规读出放大器 电路和每个参考电路。

公开(公告)号：US09479174B2

公开(公告)日：2016-10-25

申请号：US14364923

申请日：2012-12-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/094 ,  H01L27/088 ,  H01L27/12

CPC classification number: H03K19/09429 ,  H01L27/0886 ,  H01L27/1203 ,  H03K19/094 ,  H03K19/0941

Abstract: A tristate gate includes an output port and at least two transistors. Each of the transistors has at least a first and a second gate configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract translation: 三态门包括输出端口和至少两个晶体管。 每个晶体管具有至少第一和第二栅极，其配置为使得通过控制至少一个晶体管的阈值电压来设置输出端口上的高阻抗值（Z）。

公开(公告)号：US20150263610A1

公开(公告)日：2015-09-17

申请号：US14384129

申请日：2013-03-22

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M3/073 ,  H02M2003/078

Abstract: The invention relates to a charge pump circuit comprising: an input node for inputting a voltage to be boosted; an output node for outputting a boosted voltage; a plurality of pumping stages connected in series between the input node and the output node, each pump stage comprising at least one charge transfer transistor, wherein the at least one charge transfer transistor is a double-gate transistor comprising a first gate for turning the transistor on or off according to a first control signal applied to the first gate and a second gate for modifying the threshold voltage of the transistor according to a second control signal applied to the second gate, wherein the first and second control signals have the same phase.

Abstract translation: 本发明涉及一种电荷泵电路，包括：用于输入要升压的电压的输入节点; 用于输出升压电压的输出节点; 串联连接在所述输入节点和所述输出节点之间的多个泵浦级，每个泵级包括至少一个电荷转移晶体管，其中所述至少一个电荷转移晶体管是双栅极晶体管，包括用于转换晶体管的第一栅极 根据施加到第一栅极的第一控制信号的第一控制信号，以及施加到第二栅极的第二控制信号修改晶体管的阈值电压的第二栅极，其中第一和第二控制信号具有相同的相位。

公开(公告)号：US09390771B2

公开(公告)日：2016-07-12

申请号：US14372345

申请日：2013-01-16

Applicant: SOITEC

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.

Abstract translation: 一种用于感测一对双信号线上的电压差的电路，包括与第一信号线互补的第一信号线和第二信号线，包括：一对交叉耦合的反相器，布置在第一和第二信号线之间 每个反相器具有上拉晶体管和下拉晶体管，上拉晶体管或下拉晶体管的源极分别连接到第一和第二拉电压信号，解码晶体管具有源极和 分别耦合到第一和第二信号线之一的漏极端子和由解码控制信号控制的栅极，由此当解码晶体管由解码控制信号导通时，在第一和第二信号线之间建立短路 电流从第一和第二拉电压信号之一流过，从而在第一和第二拉电压信号之间产生干扰。

公开(公告)号：US20160086652A1

公开(公告)日：2016-03-24

申请号：US14785955

申请日：2014-04-24

Applicant: SOITEC

Inventor： Roland Thewes ,  Richard Ferrant

IPC: G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/04 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4099

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array, at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract translation: 本发明涉及一种半导体存储器件，包括：至少一个读出放大器电路，用于读取从存储器阵列中的选定存储单元感测的数据，至少一个参考电路，每个参考电路是读出放大器电路的复制品， 所述参考电路提供输出物理量;调节网络，向每个读出放大器电路和每个参考电路提供调节信号，其中调节信号是根据输出物理量随时间和/或空间的平均得出的，其中， 调节网络包括：控制单元，被配置为将参考电路的每个输出的物理量与目标平均值相加，所述控制单元基于所述和传送调节信号，所述调节信号馈送到每个常规读出放大器电路 和每个参考电路。

公开(公告)号：US09251871B2

公开(公告)日：2016-02-02

申请号：US14358193

申请日：2012-11-14

Applicant: SOITEC

Inventor： Richard Ferrant ,  Joerg Vollrath ,  Roland Thewes ,  Wolfgang Hoenlein ,  Hofmann Franz ,  Gerhard Enders

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract translation: 本发明涉及用于感测和放大存储在存储单元中的数据的读出放大器，该读出放大器连接在位线（BL）和与第一位线的基准位线互补（/ BL）之间，并且包括：感测 电路（SC）能够提供指示存储在存储单元中的数据的输出; 以及预充电和解码电路（PDC），包括一对双栅极晶体管（T5，T6），用于在预充电操作期间对第一和第二位线进行预充电，并将由感测电路提供的输出传送到数据线（LIO， / LIO）。

公开(公告)号：US20150035562A1

公开(公告)日：2015-02-05

申请号：US14381544

申请日：2013-02-22

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/177 ,  H03K19/003 ,  H03K19/00

CPC classification number: H03K19/17728 ,  H01L2924/0002 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/17792 ,  H01L2924/00

Abstract: The present invention relates to a look-up table architecture and to an FPGA comprising the same. The look-up table architecture comprises a registers group comprising a plurality of registers configured to issue register signals, and a programmable logic comprising a plurality of pass gates configured to be controlled at least by the register signals, the registers group and the programmable logic forming a look-up table, wherein the pass gates are placed in a single direction.

Abstract translation: 本发明涉及一种查询表架构和一种包括该查询表架构的FPGA。 查找表架构包括一个寄存器组，包括配置成发出寄存器信号的多个寄存器，以及一个可编程逻辑，包括多个通道，其配置为至少由寄存器信号，寄存器组和可编程逻辑形成 一个查找表，其中通过门被放置在单个方向上。

公开(公告)号：US20140340118A1

公开(公告)日：2014-11-20

申请号：US14364923

申请日：2012-12-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/094 ,  H01L27/12 ,  H01L27/088

CPC classification number: H03K19/09429 ,  H01L27/0886 ,  H01L27/1203 ,  H03K19/094 ,  H03K19/0941

Abstract: The present invention relates to a tristate gate (1000, 2000) comprising an output port (1400) and at least two transistors (1200, 1300; 2200, 2300), each having at least a first and a second gate, configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Abstract translation: 本发明涉及包括输出端口（1400）和至少两个晶体管（1200,1300,2200,2300）的三态门（1000,2000），每个至少具有第一和第二栅极，其被配置为使得 通过控制至少一个晶体管的阈值电压来设定输出端口上的高阻抗值（Z）。

公开(公告)号：US20150042381A1

公开(公告)日：2015-02-12

申请号：US14385436

申请日：2013-02-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: G11C16/10 ,  H03K19/177

CPC classification number: G11C16/10 ,  G11C16/045 ,  H03K19/1776

Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.

Abstract translation: 本发明涉及一种寄存器单元，包括一个输出节点，至少两个电源节点，以及第一闪存晶体管和第二闪存晶体管，其中该寄存器单元被配置为使得输出节点能够被至少一个 电源节点作为存储在至少一个闪存晶体管中的值的函数。 本发明还涉及包括寄存器单元的FPGA。