Invention Grant
- Patent Title: Fan-out wafer level packaging structure
- Patent Title (中): 扇出晶圆级封装结构
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Application No.: US14605779Application Date: 2015-01-26
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Publication No.: US09484307B2Publication Date: 2016-11-01
- Inventor: Chung-Hsuan Tsai , Chuehan Hsieh
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaosiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaosiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu; Angela D. Murch
- Main IPC: H01L23/04
- IPC: H01L23/04 ; H01L23/538 ; H01L23/31 ; H01L23/00 ; H01L25/065

Abstract:
Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and a first passivation layer; a second die including a second pad and a second passivation layer; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer includes: a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and a third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer.
Public/Granted literature
- US20160218063A1 FAN -OUT WAFER LEVEL PACKAGING STRUCTURE Public/Granted day:2016-07-28
Information query
IPC分类: