Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled.