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    Dual channel memory
    4.
    发明授权
    Dual channel memory 有权
    双通道内存

    公开(公告)号：US09466731B2

    公开(公告)日：2016-10-11

    申请号：US14457960

    申请日：2014-08-12

    Applicant: Empire Technology Development LLC

    Inventor： Zhijiong Luo

    IPC: H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  G11C11/56 ,  H01L21/84 ,  H01L21/28 ,  H01L27/115 ,  H01L27/12

    CPC classification number: H01L29/7887 ,  G11C11/5621 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883

    Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.

    Abstract translation: 技术通常被描述为涉及双通道存储器件，系统和制造方法。 各种描述的器件包括通过形成在半导体器件的双栅极结构下方的衬底来利用前通道和后通道。 在栅极结构的相对侧上使用两对触点，其中接触对形成在半导体器件的不同掺杂层上，可以将多个位存储在用作单个存储器单元的半导体器件中。 存储可以通过在浮动栅极上存储不同数量或类型的电荷来实现，其中电荷可能影响器件的通道的导通状态。 通过检测通道的导通状态，例如开路，闭路或高电阻，低电阻，可以检测存储在设备上的数据（“0”或“1”）。

    DUAL CHANNEL MEMORY
    8.
    发明申请
    DUAL CHANNEL MEMORY 有权
    双通道记忆

    公开(公告)号：US20160372602A1

    公开(公告)日：2016-12-22

    申请号：US15252250

    申请日：2016-08-31

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Zhijiong Luo

    IPC: H01L29/788 ,  H01L29/78 ,  H01L27/12 ,  G11C16/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/115 ,  H01L21/28

    CPC classification number: H01L29/7887 ,  G11C11/5621 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883

    Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.

    Abstract translation: 技术通常被描述为涉及双通道存储器件，系统和制造方法。 各种描述的器件包括通过形成在半导体器件的双栅极结构下方的衬底来利用前通道和后通道。 在栅极结构的相对侧上使用两对触点，其中接触对形成在半导体器件的不同掺杂层上，可以将多个位存储在用作单个存储器单元的半导体器件中。 存储可以通过在浮动栅极上存储不同数量或类型的电荷来实现，其中电荷可能影响器件的通道的导通状态。 通过检测通道的导通状态，例如开路，闭路或高电阻，低电阻，可以检测存储在设备上的数据（“0”或“1”）。

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