发明授权
- 专利标题： Programmable synchronous clock divider
- 专利标题（中）： 可编程同步时钟分频器
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申请号： US14617950申请日： 2015-02-10
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公开(公告)号： US09490777B2公开(公告)日： 2016-11-08
- 发明人: Inayat Ali , Puneet Dodeja , Sachin Jain
- 申请人： Inayat Ali , Puneet Dodeja , Sachin Jain
- 申请人地址： US TX Austin
- 专利权人： FREESCALE SEMICONDUCTOR,INC.
- 当前专利权人： FREESCALE SEMICONDUCTOR,INC.
- 当前专利权人地址： US TX Austin
- 代理商 Charles E. Bergere
- 主分类号： H03K21/00
- IPC分类号： H03K21/00 ; H03K3/017 ; H03K23/00 ; H03K21/02 ; H03K21/10
摘要：
A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
公开/授权文献
- US20160233852A1 PROGRAMMABLE SYNCHRONOUS CLOCK DIVIDER 公开/授权日：2016-08-11
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