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公开(公告)号：US09465404B2
公开(公告)日：2016-10-11
申请号：US14452535
申请日：2014-08-06
申请人： Inayat Ali , Arvind Kaushik , Sachin Prakash , Arindam Sinha
发明人： Inayat Ali , Arvind Kaushik , Sachin Prakash , Arindam Sinha
摘要： A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.
摘要翻译： 传输节点包括提供用于基于JESD204B的数据传输的功能时钟的数字前端设备。 前端装置包括用于基于前端装置的装置时钟产生锁相时钟的PLL，用于通过分相锁相时钟产生功能时钟的时钟分割部，连接在PLL之间的时钟门控装置 和时钟分割单元，以及用于定时无线帧边界的系统参考信号采样单元。 时钟门控单元门锁相锁定时钟，以便在锁定PLL或接收系统重新同步请求时，将功能时钟与相位锁定时钟的预定数量周期内的器件时钟对准。 系统参考信号采样单元在设备时钟和锁相时钟之间以零周期等待时间采样系统参考信号。
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公开(公告)号：US20160041579A1
公开(公告)日：2016-02-11
申请号：US14452535
申请日：2014-08-06
申请人： Inayat Ali , Arvind Kaushik , Sachin Prakash , Arindam Sinha
发明人： Inayat Ali , Arvind Kaushik , Sachin Prakash , Arindam Sinha
摘要： A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.
摘要翻译： 传输节点包括提供用于基于JESD204B的数据传输的功能时钟的数字前端设备。 前端装置包括用于基于前端装置的装置时钟产生锁相时钟的PLL，用于通过分相锁相时钟产生功能时钟的时钟分割部，连接在PLL之间的时钟门控装置 和时钟分割单元，以及用于定时无线帧边界的系统参考信号采样单元。 时钟门控单元门锁相锁定时钟，以便在锁定PLL或接收系统重新同步请求时，将功能时钟与相位锁定时钟的预定数量周期内的器件时钟对准。 系统参考信号采样单元在设备时钟和锁相时钟之间以零周期等待时间采样系统参考信号。
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公开(公告)号：US20160233852A1
公开(公告)日：2016-08-11
申请号：US14617950
申请日：2015-02-10
申请人： Inayat Ali , Puneet Dodeja , Sachin Jain
发明人： Inayat Ali , Puneet Dodeja , Sachin Jain
CPC分类号： H03K3/017 , H03K5/1565 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/002
摘要： A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
摘要翻译： 从输入时钟信号产生分频时钟信号。 通过基于占空比输入的值和输入时钟信号的除法产生比较值来编程分频时钟信号的占空比。 将比较值与计数值进行比较，以生成短和长脉冲信号。 基于短脉冲信号和长脉冲信号产生分频时钟信号。 分频时钟信号的占空比根据比较值而变化。
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公开(公告)号：US08829953B1
公开(公告)日：2014-09-09
申请号：US14151790
申请日：2014-01-09
申请人： Inayat Ali , Sachin Jain , Kanishka Patwal
发明人： Inayat Ali , Sachin Jain , Kanishka Patwal
CPC分类号： H03K21/026 , H03K21/10 , H03K23/667
摘要： A programmable clock divider includes first and second comparators for generating first and second signals respectively based on a count value of a counter and a frequency ratio value. First and second flip-flops delay the first and second signals by one clock cycle of the input clock signal. An active-low latch delays the second signal by half a clock cycle of the input clock signal. A multiplexer receives the delayed first and second signals at first and second input terminals respectively and the input clock signal at a select terminal, and generates a divided clock signal. The multiplexer outputs the second delayed signal when the input clock signal is at a logic high state and outputs the first delayed signal when the input clock signal is at a logic low state.
摘要翻译： 可编程时钟分频器包括分别基于计数器的计数值和频率比值产生第一和第二信号的第一和第二比较器。 第一和第二触发器将第一和第二信号延迟输入时钟信号的一个时钟周期。 低电平有效锁存器将第二个信号延迟半个时钟周期的输入时钟信号。 多路复用器在第一和第二输入端分别接收延迟的第一和第二信号，并在选择端接收输入时钟信号，并产生分频时钟信号。 当输入时钟信号处于逻辑高电平状态时，多路复用器输出第二延迟信号，并在输入时钟信号处于逻辑低电平状态时输出第一延迟信号。
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公开(公告)号：US09490777B2
公开(公告)日：2016-11-08
申请号：US14617950
申请日：2015-02-10
申请人： Inayat Ali , Puneet Dodeja , Sachin Jain
发明人： Inayat Ali , Puneet Dodeja , Sachin Jain
CPC分类号： H03K3/017 , H03K5/1565 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/002
摘要： A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
摘要翻译： 从输入时钟信号产生分频时钟信号。 通过基于占空比输入的值和输入时钟信号的除法产生比较值来编程分频时钟信号的占空比。 将比较值与计数值进行比较，以生成短和长脉冲信号。 基于短脉冲信号和长脉冲信号产生分频时钟信号。 分频时钟信号的占空比根据比较值而变化。
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