Invention Grant
US09496234B1 Wafer-level chip-scale package structure utilizing conductive polymer
有权
使用导电聚合物的晶圆级芯片级封装结构
- Patent Title: Wafer-level chip-scale package structure utilizing conductive polymer
- Patent Title (中): 使用导电聚合物的晶圆级芯片级封装结构
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Application No.: US14741802Application Date: 2015-06-17
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Publication No.: US09496234B1Publication Date: 2016-11-15
- Inventor: Richard S. Graf , Kibby B. Horsford , Sudeep Mandal
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00
Abstract:
An integrated conductive polymer-solder ball structure is provided. The integrated conductive polymer-solder ball structure comprises a sputter seed layer applied to a wafer structure, one or more conductive polymer pad structures applied to the sputtered seed layer at locations on the wafer structure where one or more solder ball structures will be formed, an electroplating layer applied to portions of the one or more conductive polymer pad structures where a photoresist layer has been exposed, and a solder ball formed on each of the electroplating layers thereby forming the one or more solder ball structures.
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