Invention Grant
US09507596B2 Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources
有权
基于对数据源的内存访问计数的预取器调节的指令和逻辑
- Patent Title: Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources
- Patent Title (中): 基于对数据源的内存访问计数的预取器调节的指令和逻辑
-
Application No.: US14471261Application Date: 2014-08-28
-
Publication No.: US09507596B2Publication Date: 2016-11-29
- Inventor: Ashok Jagannathan , Prabhat Jain , Krishna N. Vinod , Avinash Sodani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Baker Botts L.L.P.
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F9/30 ; G06F12/08 ; G06F9/38 ; G06F12/06
Abstract:
A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.
Public/Granted literature
- US20160062768A1 INSTRUCTION AND LOGIC FOR PREFETCHER THROTTLING BASED ON DATA SOURCE Public/Granted day:2016-03-03
Information query
