Method to form silicide and contact at embedded epitaxial facet

Invention Grant

US09508601B2 Method to form silicide and contact at embedded epitaxial facet 有权

Title translation: 在嵌入式外延面形成硅化物和接触的方法

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Patent Title: Method to form silicide and contact at embedded epitaxial facet
Patent Title (中): 在嵌入式外延面形成硅化物和接触的方法
Application No.: US14563062

Application Date: 2014-12-08
Publication No.: US09508601B2

Publication Date: 2016-11-29
Inventor: Kwan-Yong Lim , James Walter Blatchford , Shashank S. Ekbote , Younsung Choi
Applicant: Texas Instruments Incorporated
Applicant Address: US TX Dallas
Assignee: TEXAS INSTRUMENTS INCORPORATED
Current Assignee: TEXAS INSTRUMENTS INCORPORATED
Current Assignee Address: US TX Dallas
Agent Jacqueline J. Garner; Frank D. Cimino
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L29/66 ; H01L21/8234

Method to form silicide and contact at embedded epitaxial facet

Abstract:

An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract(Chinese):

在MOS间隔填充有二氧化硅的间隙填料，形成与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。在暴露的外延源极/漏极区上形成金属硅化物。在集成电路上形成CESL，并且在CESL上形成PMD层。通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

Public/Granted literature

US20150170972A1 METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET Public/Granted day:2015-06-18

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS