Invention Grant
US09508615B2 Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
有权
时钟树综合,用于3D集成电路的低成本预绑定测试
- Patent Title: Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
- Patent Title (中): 时钟树综合,用于3D集成电路的低成本预绑定测试
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Application No.: US14617901Application Date: 2015-02-09
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Publication No.: US09508615B2Publication Date: 2016-11-29
- Inventor: Sung Kyu Lim , Kambiz Samadi , Pratyush Kamal , Yang Du
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L21/66 ; H01L25/065 ; H01L25/00 ; H01L23/538

Abstract:
To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.
Public/Granted literature
- US20160233134A1 CLOCK TREE SYNTHESIS FOR LOW COST PRE-BOND TESTING OF 3D INTEGRATED CIRCUITS Public/Granted day:2016-08-11
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