公开(公告)号：US20160258996A1

公开(公告)日：2016-09-08

申请号：US14639511

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Ratibor Radojcic ,  Yang Du

IPC: G01R31/28 ,  H01L27/06 ,  G01R19/165 ,  H01L23/58 ,  H01L23/64 ,  H01L21/66 ,  H01L23/48

CPC classification number: G01R31/2851 ,  G01R19/16533 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/585 ,  H01L23/647 ,  H01L27/0688

Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

Abstract translation: 公开了用于检测三维（3D）集成电路（IC）（3DIC）中的TSV裂纹的穿通硅通孔（TSV）裂纹传感器以及相关方法和系统。 在一个方面，提供一种TSV裂纹传感器电路，其中用于多个TSV的掺杂环并联互连，使得所有互连的TSV掺杂环可以同时测试，通过向互连的掺杂的触点提供单个电流 戒指。 另一方面，提供包括一个或多个冗余TSV的TSV裂纹传感器电路。 用于对应的TSV的每个掺杂环被独立地测试，并且可以用未检测到其掺杂环被破裂的备用TSV来替换有缺陷的TSV。 该电路允许通过用备用TSV替换可能受损的TSV来校正受损的3DIC。

公开(公告)号：US09483598B2

公开(公告)日：2016-11-01

申请号：US14617896

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0688

Abstract: An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

Abstract translation: 用于三维（3D）集成电路的知识产权（IP）块设计方法可以包括将具有一个或多个电路组件的至少一个二维（2D）块折叠到具有多个层的3D块中，其中， 折叠的2D块中的多个电路组件可以分布在3D块中的多个层中。 此外，一个或多个引脚可以跨越3D块中的多个层复制，并且一个或多个复制引脚可以使用放置在3D块内部的一个或多个块内穿通硅通孔（TSV）彼此连接 。

公开(公告)号：US09569380B2

公开(公告)日：2017-02-14

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L23/48 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

公开(公告)号：US09508615B2

公开(公告)日：2016-11-29

申请号：US14617901

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/58 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。

公开(公告)号：US20160267214A1

公开(公告)日：2016-09-15

申请号：US14643096

申请日：2015-03-10

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Francois Ibrahim Atallah ,  Rashid Ahmed Akbar Attar ,  Keith Alan Bowman ,  Yang Du ,  Juzer Zainuddin Fatehi ,  Jai Ganesh Kumar ,  Yu Pu ,  Giby Samson ,  Kendrick Hoy Leong Yuen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/62 ,  G06F2217/84

Abstract: Clock tree design methods for ultra-wide voltage range circuits are disclosed. In one aspect, place and route software creates an integrated circuit (IC) in an optimal configuration at a first voltage condition. A first clock tree is created as part of the place and route process. Clock skew for the first clock tree is evaluated and minimized through insertion of bypassable delay elements. The delay elements are then removed from the wiring routing diagram. A second voltage condition is identified, and clock tree generation software is allowed to optimize the wiring routing diagram for the second voltage condition. The second clock tree generation software may insert more bypassable delay elements into the wiring routing diagram that allow clock skew optimization at the second voltage condition. The initial bypassable delay elements are then reinserted into the wiring routing diagram and a finished IC is established.

Abstract translation: 公开了用于超宽电压范围电路的时钟树设计方法。 在一个方面，放置和路由软件在第一电压条件下以最佳配置创建集成电路（IC）。 第一个时钟树是作为地点和路由过程的一部分而创建的。 通过插入可旁路延迟元件来评估和最小化第一个时钟树的时钟偏移。 然后将延迟元件从布线图中删除。 识别出第二电压条件，并允许时钟树生成软件优化第二电压条件的布线布线图。 第二个时钟树生成软件可以在布线布线图中插入更多的可旁路延迟元件，允许在第二电压条件下进行时钟偏移优化。 然后将初始可旁路延迟元件重新插入到布线布线图中，并建立成品IC。

公开(公告)号：US09869713B2

公开(公告)日：2018-01-16

申请号：US14639511

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Ratibor Radojcic ,  Yang Du

IPC: G01R31/02 ,  G01R31/28 ,  G01R19/165 ,  H01L23/48 ,  H01L23/58 ,  H01L23/64 ,  H01L27/06 ,  H01L21/66 ,  G01R31/3185

CPC classification number: G01R31/2851 ,  G01R19/16533 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/585 ,  H01L23/647 ,  H01L27/0688

Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

公开(公告)号：US09741691B2

公开(公告)日：2017-08-22

申请号：US14698842

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Yang Du

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L27/06 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05147 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73153 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.

公开(公告)号：US09626311B2

公开(公告)日：2017-04-18

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L23/48 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/4282 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06544

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

公开(公告)号：US20160217087A1

公开(公告)日：2016-07-28

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L25/00 ,  H01L23/50 ,  H01L23/48 ,  H01L25/18

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/4282 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06544

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract translation: 在详细描述中公开的方面包括采用分布式硅通孔（TSV）农场的三维（3D）集成电路（IC）（3DIC）中的存储器控​​制器放置。 在这方面，在一方面，存储器控制器基于分布式TSV场内的集中式存储器控制器放置方案而设置在3DIC中。 存储器控制器可以放置在多个TSV农场中的几何中心处，以在存储器控制器和多个TSV农场中的每一个之间提供大致相等的线长度。 在另一方面，基于分布式存储器控制器放置方案在3DIC中提供多个存储器控制器，其中多个存储器控制器中的每一个与多个TSV农场中的相应TSV场相邻放置。 通过在3DIC中基于集中式存储器控制器放置方案和/或分布式存储器控制器放置方案布置存储器控制器，存储器访问请求的等待时间最小化。

公开(公告)号：US09256246B1

公开(公告)日：2016-02-09

申请号：US14608462

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Yang Du

IPC: H03H11/26 ,  H03K5/12 ,  G06F1/10 ,  H03K5/135 ,  H03K5/00

CPC classification number: G06F1/10 ,  H01L27/0688 ,  H03K5/135 ,  H03K2005/00019

Abstract: Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) is disclosed. In one aspect, a sensor is placed on each tier of a 3DIC to evaluate a speed characteristic of each tier relative to the speed characteristic of another tier. Based on determining the relative speed characteristics, a control signal may be provided to adjust back body bias elements for clock buffers. Adjusting the back body bias effectively adjusts a threshold voltage of the clock buffers. Adjusting the threshold voltage of the clock buffers has the effect of slowing down or speeding up the clock buffers. For example, slow clock buffers may be sped up by providing a forward body bias and fast clock buffers may be slowed down by providing a reverse body bias. By speeding up slow elements and slowing down fast elements, compensation for the relative speed characteristics may be provided.

Abstract translation: 公开了具有三维（3D）集成电路（IC）（3DIC）中的自适应主体偏置的时钟偏移补偿。 在一个方面，将传感器放置在3DIC的每个层上，以评估每个层相对于另一层的速度特性的速度特性。 基于确定相对速度特性，可以提供控制信号来调整用于时钟缓冲器的背部偏置元件。 调整背面偏置有效地调整时钟缓冲器的阈值电压。 调整时钟缓冲器的阈值电压具有减慢或加速时钟缓冲器的作用。 例如，可以通过提供正向偏置来加速慢时钟缓冲器，并且可以通过提供反向体偏置来减慢快速时钟缓冲器。 通过加快缓慢的元素和减缓快速元素，可以提供相对速度特性的补偿。