Invention Grant
- Patent Title: Mounting method
- Patent Title (中): 安装方法
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Application No.: US14420181Application Date: 2013-03-11
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Publication No.: US09508679B2Publication Date: 2016-11-29
- Inventor: Mitsuhiko Ueda , Yoshiharu Sanagawa , Takanori Aketa , Shintaro Hayashi
- Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2012-176279 20120808
- International Application: PCT/JP2013/001558 WO 20130311
- International Announcement: WO2014/024343 WO 20140213
- Main IPC: H01L23/00
- IPC: H01L23/00 ; B23K20/00 ; H01L21/52 ; H01L21/683

Abstract:
A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips. First basic process includes a first step and a second step. First step is to align, on a first metal layer of the substrate, a second metal layer of each chip. Second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. Main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips. Second basic process includes a third step and a fourth step. Third step is to recognize a position of each chip temporarily mounted on the substrate. Fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding.
Public/Granted literature
- US20150287696A1 MOUNTING METHOD Public/Granted day:2015-10-08
Information query
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