A thin film transistor display panel includes: a substrate; a gate line and a storage electrode line on the substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line, a drain electrode and a divided-voltage reference voltage line on the semiconductor layer; a passivation layer covering the data line, the drain electrode and the divided-voltage reference voltage line; and a first sub-pixel electrode and a second sub-pixel electrode electrically connected to the drain electrode through a contact hole defined in the passivation layer and including a plurality of pixel branch electrodes, where the divided-voltage reference voltage line divides a first or second sub-pixel area, which is defined by the first or second sub-pixel electrode, into two regions, and each of the two regions has three sides defined by the divided-voltage reference voltage line and an open side.