Invention Grant
- Patent Title: L2 cache retention mode
- Patent Title (中): L2缓存保留模式
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Application No.: US14224773Application Date: 2014-03-25
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Publication No.: US09513693B2Publication Date: 2016-12-06
- Inventor: Prashant Jain , Brian P. Lilly , Mahnaz Sadoughi-Yarandi , Helen Huang
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Rory D. Rankin
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G11C7/12 ; G06F12/08

Abstract:
Systems and methods for reducing leakage power in a L2 cache within a SoC. The L2 cache is partitioned into multiple banks, and each bank has its own separate power supply. An idle counter is maintained for each bank to count a number of cycles during which the bank has been inactive. The temperature and leaky factor of the SoC are used to select an operating point of the SoC. Based on the operating point, an idle counter threshold is set, with a high temperature and high leaky factor corresponding to a relatively low idle counter threshold, and with a low temperature and low leaky factor corresponding to a relatively high idle counter threshold. When a given idle counter exceeds the idle counter threshold, the voltage supplied to the corresponding bank is reduced to a voltage sufficient for retention of data but not for access.
Public/Granted literature
- US20150277541A1 L2 CACHE RETENTION MODE Public/Granted day:2015-10-01
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