Invention Grant
- Patent Title: On-package input/output architecture
- Patent Title (中): 封装输入/输出架构
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Application No.: US13995007Application Date: 2011-12-22
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Publication No.: US09519609B2Publication Date: 2016-12-13
- Inventor: Thomas P. Thomas , Rajesh Kumar
- Applicant: Thomas P. Thomas , Rajesh Kumar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/066971 WO 20111222
- International Announcement: WO2013/095536 WO 20130627
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/38

Abstract:
An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
Public/Granted literature
- US20130318266A1 ON-PACKAGE INPUT/OUTPUT ARCHITECTURE Public/Granted day:2013-11-28
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