发明授权
US09520350B2 Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
有权
无创积层(BBUL)半导体封装,具有超薄介电层
- 专利标题: Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
- 专利标题(中): 无创积层(BBUL)半导体封装,具有超薄介电层
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申请号: US13801859申请日: 2013-03-13
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公开(公告)号: US09520350B2公开(公告)日: 2016-12-13
- 发明人: Weng Hong Teh , Emile Davies-Venn , Ebrahim Andideh , Digvijay A. Raorane , Daniel N. Sobieski
- 申请人: Weng Hong Teh , Emile Davies-Venn , Ebrahim Andideh , Digvijay A. Raorane , Daniel N. Sobieski
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L23/532 ; H01L21/768 ; H01L23/00
摘要:
Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.
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