Invention Grant
US09530864B2 Junction overlap control in a semiconductor device using a sacrificial spacer layer
有权
在使用牺牲隔离层的半导体器件中的结重叠控制
- Patent Title: Junction overlap control in a semiconductor device using a sacrificial spacer layer
- Patent Title (中): 在使用牺牲隔离层的半导体器件中的结重叠控制
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Application No.: US14314404Application Date: 2014-06-25
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Publication No.: US09530864B2Publication Date: 2016-12-27
- Inventor: Steven J. Bentley , Michael J. Hargrove , Chia-Yu Chen , Ryan O. Jung , Sivanandha K. Kanakasabapathy , Tenko Yamashita
- Applicant: GLOBALFOUNDRIES Inc. , International Business Machines Corporation
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78

Abstract:
Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.
Public/Granted literature
- US20150380514A1 JUNCTION OVERLAP CONTROL IN A SEMICONDUCTOR DEVICE USING A SACRIFICIAL SPACER LAYER Public/Granted day:2015-12-31
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